SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 30

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

9.5
9.6
9.7
30
Power Management Controller
Periodic Interval Timer
Watchdog Timer
AT91SAM9263
Figure 9-3.
• Provides:
• Five flexible operating modes:
• Includes a 20-bit Periodic Counter, with less than 1 µs accuracy
• Includes a 12-bit Interval Overlay Counter
• Real-time OS or Linux
• 16-bit key-protected Counter, programmable only once
– the Processor Clock PCK
– the Master Clock MCK, in particular to the Matrix and the memory interfaces
– the USB Device Clock UDPCK
– the USB Host Clock UHPCK
– independent peripheral clocks, typically at the frequency of MCK
– four programmable clock outputs: PCK0 to PCK3
– Normal Mode with processor and peripherals running at a programmable frequency
– Idle Mode with processor stopped while waiting for an interrupt
– Slow Clock Mode with processor and peripherals running at low frequency
– Standby Mode, mix of Idle and Backup Mode, with peripherals running at low
– Backup Mode with Main Power Supplies off, VDDBU powered by a battery
frequency, processor stopped waiting for an interrupt
PLLBCK
MAINCK
PLLACK
AT91SAM9263 Power Management Controller Block Diagram
SLCK
Master Clock Controller
®
/WindowsCE
/1,/2,/4,...,/64
Prescaler
MAINCK
PLLACK
PLLBCK
PLLBCK
SLCK
Programmable Clock Controller
®
compliant tick generator
Divider
/1,/2,/4
USB Clock Controller
Divider
/1,/2,/4
/1,/2,/4,...,/64
Prescaler
ON/OFF
Clock Controller
Processor
Controller
Idle Mode
ON/OFF
Clock
Peripherals
ON/OFF
MCK
PCK
int
periph_clk[..]
pck[..]
UDPCK
UHPCK
6249I–ATARM–3-Oct-11