SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 369

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

28.9.10
Register Name:CKGR_PLLBR
Address:
Access Type:Read-write
Possible limitations on PLLB input frequencies and multiplier factors should be checked before using the PMC.
• DIVB Divider B
• PLLBCOUNT: PLL B Counter
Specifies the number of slow clock cycles before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written.
• OUTB: PLL B Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Char-
acteristics section of the product datasheet.
• MULB: PLL B Multiplier
0 = The PLL B is deactivated.
1 up to 2047 = The PLL B Clock frequency is the PLL B input frequency multiplied by MULB + 1.
• USBDIV: Divider for USB Clock
6249I–ATARM–3-Oct-11
DIVB
0
1
2 - 255
31
23
15
–
7
0
0
1
1
PMC Clock Generator PLL B Register
OUTB
0xFFFFFC2C
USBDIV
30
22
14
–
6
0
1
0
1
29
21
13
5
USBDIV
Divider Selected
Divider output is 0
Divider is bypassed
Divider output is the selected clock divided by DIVB.
Divider for USB Clock(s)
Divider output is PLLB clock output.
Divider output is PLLB clock output divided by 2.
Divider output is PLLB clock output divided by 4.
Reserved.
28
20
12
4
MULB
DIVB
27
19
11
–
3
PLLBCOUNT
26
18
10
2
AT91SAM9263
MULB
25
17
9
1
24
16
8
0
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