SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 310

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

0 = Hardware handshaking interface. Software-initiated transaction requests are ignored.
1 = Software handshaking interface. Hardware-initiated transaction requests are ignored.
If the source peripheral is memory, then this bit is ignored.
• LOCK_CH_L: Channel Lock Level
Indicates the duration over which DMAC_CFGx.LOCK_CH bit applies.
00 = Over complete DMA transfer
01 = Over complete DMA block transfer
1x = Over complete DMA transaction
• LOCK_B_L: Bus Lock Level
Indicates the duration over which DMAC_CFGx.LOCK_B bit applies.
00 = Over complete DMA transfer
01 = Over complete DMA block transfer
1x = Over complete DMA transaction
• LOCK_CH: Channel Lock Bit
When the channel is granted control of the master bus interface and if the DMAC_CFGx.LOCK_CH bit is asserted, then no
other channels are granted control of the master bus interface for the duration specified in DMAC_CFGx.LOCK_CH_L.
Indicates to the master bus interface arbiter that this channel wants exclusive access to the master bus interface for the
duration specified in DMAC_CFGx.LOCK_CH_L.
• LOCK_B: Bus Lock Bit
When active, the AMBA bus master signal hlock is asserted for the duration specified in DMAC_CFGx.LOCK_B_L.
• DS_HS_POL: Destination Handshaking Interface Polarity
0 = Active high
1 = Active low
• SR_HS_POL: Source Handshaking Interface Polarity
0 = Active high
1 = Active low
• MAX_ABRST: Maximum AMBA Burst Length
Maximum AMBA burst length that is used for DMA transfers on this channel. A value of ‘0’ indicates that software is not lim-
iting the maximum AMBA burst length for DMA transfers on this channel.
• RELOAD_SR: Automatic Source Reload
The DMAC_SARx register can be automatically reloaded from its initial value at the end of every block for multi-block trans-
fers. A new block transfer is then initiated.
• RELOAD_DS: Automatic Destination Reload
The DMAC_DARx register can be automatically reloaded from its initial value at the end of every block for multi-block
transfers. A new block transfer is then initiated.
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6249I–ATARM–3-Oct-11