SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 198

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

23.5.3
Figure 23-4. Read Burst with Boundary Row Access
6249I–ATARM–3-Oct-11
SDRAMC_A[12:0]
D[31:0]
SDWE
SDCS
SDCK
RAS
CAS
Border Management
col a
Row n
col b
Dna
When the memory row boundary has been reached, an automatic page break is inserted. In this
case, the SDRAM controller generates a precharge command, activates the new row and ini-
tiates a read or write command. To comply with SDRAM timing parameters, an additional clock
cycle is inserted between the precharge/active (t
mand. This is described in
col c
Dnb
col d
Dnc
Dnd
T
Figure 23-4
RP
= 3
Row m
below.
T
RCD
= 3
RP
col a
) command and the active/read (t
CAS = 2
col b
Dma
col c
AT91SAM9263
Dmb
col d
Dmc
col e
Dmd
RCD
Dme
) com-
240