DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 1007

• Manufacturer Part Number: DF2148RTE20IV
• Description: MCU 5V 128K I-TEMP,PB-FREE, 100-
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148RTE20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

A.4
The tables in this section can be used to calculate the number of states required for instruction
execution by the H8S/2000 CPU. Table A.5 shows the number of instruction fetch, data
read/write, and other cycles occurring in each instruction, and table A.4 shows the number of
states required per cycle according to the bus size. The number of states required for execution of
an instruction can be calculated from these two tables as follows:
Examples of Calculation of Number of States Required for Execution
Examples: Advanced mode, stack located in external address space, on-chip supporting modules
accessed in two states with 8-bit bus width, external devices accessed in three states with one wait
state and 16-bit bus width.
1. BSET #0,@FFFFC7:8
2. JSR @@30
From table A.5,
From table A.4,
Number of states = 2
From table A.5,
From table A.4,
Number of states = 2
Number of states = I
I = L = 2 and J = K = M = N = 0
S
I = J = K = 2 and L = M = N = 0
S
Number of States Required for Execution
I
I
= 4 and S
= S
J
= S
K
= 4
L
= 2
4 + 2
4 + 2
S
I
+ J
2 = 12
4 + 2
S
J
+ K
4 = 24
S
K
+ L
Rev. 4.00 Sep 27, 2006 page 961 of 1130
S
L
+ M
S
M
+ N
Appendix A Instruction Set
S
N
REJ09B0327-0400