DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 359

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Table 11.3 Buffered Input Capture Edge Selection (Example)
To ensure input capture, the width of the input capture pulse should be at least 1.5 system clock
periods (1.5 ). When triggering is enabled on both edges, the input capture pulse width should be
at least 2.5 system clock periods (2.5 ).
ICR is initialized to H'0000 by a reset and in hardware standby mode.
11.2.4
OCRAR and OCRAF are 16-bit readable/writable registers.
When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use
of OCRAR and OCRAF. The contents of OCRAR and OCRAF are automatically added
alternately to OCRA, and the result is written to OCRA. The write operation is performed on the
occurrence of compare-match A. In the first compare-match A after the OCRAMS bit is set to 1,
OCRAF is added.
The operation due to compare-match A varies according to whether the compare-match follows
addition of OCRAR or OCRAF. The value of the OLVLA bit in TOCR is ignored, and 1 is output
on a compare-match A following addition of OCRAF, while 0 is output on a compare-match A
following addition of OCRAR.
When the OCRA automatically addition function is used, do not set internal clock /2 as the FRC
counter input clock together with an OCRAR (or OCRAF) value of H'0001 or less.
OCRAR and OCRAF are initialized to H'FFFF by a reset and in hardware standby mode.
IEDGA
0
1
Read/
Bit
Initial
value
Write
Output Compare Registers AR and AF (OCRAR, OCRAF)
IEDGC
0
1
0
1
R/W
15
1
R/W
14
1
R/W
13
1
Description
Captured on falling edge of input capture A (FTIA)
Captured on both rising and falling edges of input capture A (FTIA)
Captured on rising edge of input capture A (FTIA)
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
Rev. 4.00 Sep 27, 2006 page 313 of 1130
7
1
Section 11 16-Bit Free-Running Timer
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
REJ09B0327-0400
R/W
2
1
(Initial value)
R/W
1
1
R/W
0
1

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