DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 445

• Manufacturer Part Number: DF2148RTE20IV
• Description: MCU 5V 128K I-TEMP,PB-FREE, 100-
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148RTE20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 13.7 Examples of TCORB, TCR, and TCSR Settings
Register
TCR in
TMR1
TCSR in
TMR1
TOCRB in TMR1
IHI signal
IVI signal (PDC signal)
IVO signal
(without fall modification,
with IHI synchronization)
IVO signal
(with fall modification
and IHI synchronization)
IVO signal
(with fall modification,
without IHI synchronization)
Figure 13.7 Fall Modification/IHI Synchronization Timing Chart
Bit(s)
7
6
5
4 and 3
2 to 0
3 to 0
Abbreviation
CMIEB
CMIEA
OVIE
CCLR1,
CCLR0
CKS2 to CKS0
OS3 to OS0
Contents
0
0
0
11
0011
1001
H'03
(example)
101
Rev. 4.00 Sep 27, 2006 page 399 of 1130
Description
Interrupts due to compare-match and
overflow are disabled
TCNT is cleared by the rising edge of the
external reset signal (inverse of the IVI
signal)
TCNT is incremented on the rising edge of
the external clock (IHI signal)
Not changed by compare-match B; output
inverted by compare-match A (toggle
output)
or
when TCORB
compare-match B, 0 output on compare-
match A
Compare-match on the 4th (example) rise
of the IHI signal after the rise of the
inverse of the IVI signal
TCNT
0
Section 13 Timer Connection
1
TCORA, 1 output on
2
3
TCNT = TCORB (3)
REJ09B0327-0400
4
5