DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 634

• Manufacturer Part Number: DF2148RTE20IV
• Description: MCU 5V 128K I-TEMP,PB-FREE, 100-
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148RTE20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 Host Interface
Bit 1—Host Interface Enable (HIE): Enables or disables CPU access to the host interface
registers. When enabled, the host interface registers (HICR, IDR1, ODR1, STR1, IDR2, ODR2,
and STR2) can be accessed.
Bit 1
HIE
0
1
18.2.2
SYSCR2 is an 8-bit readable/writable register which controls chip operations. Host interface
functions are enabled or disabled by the HI12E bit in SYSCR2. The number of channels that can
be used can be extended to a maximum of four by means of the CS3E bit and CS4E bit. SYSCR2
is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Key Wakeup Level 1 and 0 (KWUL1, KWUL0): The port 6 input level can be
set and changed by software. For details see section 8, I/O Ports.
Bit 5—Port 6 Input Pull-Up Extra (P6PUE): Controls and selects the current specification for
the port 6 MOS input pull-up function connected by means of KMPCR settings. For details see
section 8, I/O Ports.
Bit 4—Reserved: Do not write 1 to this bit.
Rev. 4.00 Sep 27, 2006 page 588 of 1130
REJ09B0327-0400
Bit
Initial value
Read/Write
System Control Register 2 (SYSCR2)
Description
Host interface register (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), CPU
access is disabled
Host interface register (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), CPU
access is enabled
KWUL1
R/W
7
0
KWUL0
R/W
6
0
P6PUE
R/W
5
0
—
—
4
0
SDE
R/W
3
0
CS4E
R/W
2
0
CS3E
R/W
1
0
(Initial value)
HI12E
R/W
0
0