DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 430

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 13 Timer Connection
Bit 5
CLOE
0
1
Bit 4
CBOE
0
1
Bits 3 to 0—Output Synchronization Signal Inversion (HOINV, VOINV, CLOINV,
CBOINV): These bits select inversion of the output phase of the horizontal synchronization signal
(HSYNCO), the vertical synchronization signal (VSYNCO), the clamp waveform (CLAMPO),
and the blank waveform (CBLANK).
Bit 3
HOINV
0
1
Bit 2
VOINV
0
1
Bit 1
CLOINV
0
1
Rev. 4.00 Sep 27, 2006 page 384 of 1130
REJ09B0327-0400
Description
The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the
P64/FTIC/KIN4/CIN4 pin
The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the CLAMPO pin
Description
The P27/A15/PW15/CBLANK pin functions as the P27/A15/PW15 pin
In mode 1 (expanded mode with on-chip ROM disabled):
The P27/A15/PW15/CBLANK pin functions as the A15 pin
In modes 2 and 3 (modes with on-chip ROM enabled):
The P27/A15/PW15/CBLANK pin functions as the CBLANK pin
Description
The IHO signal is used directly as the HSYNCO output
The IHO signal is inverted before use as the HSYNCO output
Description
The IVO signal is used directly as the VSYNCO output
The IVO signal is inverted before use as the VSYNCO output
Description
The CLO signal (CL1, CL2, CL3, or CL4 signal) is used directly as the
CLAMPO output
The CLO signal (CL1, CL2, CL3, or CL4 signal) is inverted before use as
the CLAMPO output
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)

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