DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 159

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
5.1
5.1.1
This LSI control interrupts by means of an interrupt controller. The interrupt controller has the
following features:
Two interrupt control modes
Priorities settable with ICR
Independent vector addresses
Twenty-three external interrupt pins (nine external sources)
DTC control
Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits
in the system control register (SYSCR).
An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority
levels can be set for each module for all interrupts except NMI and address break.
All interrupt sources are assigned independent vector addresses, making it unnecessary for
the source to be identified in the interrupt handling routine.
NMI is the highest-priority interrupt, and is accepted at all times. A rising or falling edge at
the NMI pin can be selected for the NMI interrupt.
Falling edge, rising edge, or both edge detection, or level sensing, at pins IRQ7 to IRQ0
can be selected for interrupts IRQ7 to IRQ0.
The IRQ6 interrupt is shared by the interrupt from the IRQ6 pin and eight external interrupt
inputs (KIN7 to KIN0), and the IRQ7 interrupt is shared by the interrupt from the IRQ7 pin
and eight external interrupt inputs (KIN15 to KIN8). KIN15 to KIN0 can be masked
individually by the user program.
DTC activation is controlled by means of interrupts.
Features
Overview
Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 113 of 1130
Section 5 Interrupt Controller
REJ09B0327-0400

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