DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 638

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 18 Host Interface
18.2.4
IDR1 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the
host processor. When CSn (n = 1 to 4) is low, information on the host data bus is written into
IDRn at the rising edge of IOW. The HA0 state is also latched into the C/D bit in STRn to indicate
whether the written information is a command or data.
The initial values of IDR1 after a reset and in standby mode are undetermined.
18.2.5
ODR1 is an 8-bit readable/writable register to the slave processor, and an 8-bit read-only register
to the host processor. The ODRn contents are output on the host data bus when HA0 is low, CSn
(n = 1 to 4) is low, and IOR is low.
The initial values of ODR1 after a reset and in standby mode are undetermined.
Rev. 4.00 Sep 27, 2006 page 592 of 1130
REJ09B0327-0400
Bit
Initial value
Slave Read/Write
Host Read/Write
Bit
Initial value
Slave Read/Write
Host Read/Write
Input Data Register 1 (IDR1)
Output Data Register 1 (ODR)
ODR7
IDR7
R/W
W
R
R
7
7
ODR6
IDR6
R/W
W
R
6
R
6
ODR5
IDR5
R/W
W
R
R
5
5
ODR4
IDR4
R/W
W
R
R
4
4
ODR3
IDR3
R/W
W
R
R
3
3
ODR2
IDR2
R/W
W
R
R
2
2
ODR1
IDR1
R/W
W
R
R
1
1
ODR0
IDR0
R/W
W
R
R
0
0

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