DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 224

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 6 Bus Controller
6.7.3
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. There are specific times at which each bus master can relinquish the bus.
CPU
The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus
arbiter transfers the bus to the DTC. The timing for transfer of the bus is as follows:
DTC
The DTC sends the bus arbiter a request for the bus when an activation request is generated.
The DTC does not release the bus until it has completed a series of processing operations.
Rev. 4.00 Sep 27, 2006 page 178 of 1130
REJ09B0327-0400
The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
discrete operations, as in the case of a longword-size access, the bus is not transferred between
the operations.
See appendix A.5, Bus States during Instruction Execution, for timings at which the bus is not
transferred.
If the CPU is in sleep mode, it transfers the bus immediately.
Bus Transfer Timing

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