DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 42

• Manufacturer Part Number: DF2148RTE20IV
• Description: MCU 5V 128K I-TEMP,PB-FREE, 100-
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148RTE20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

23.9 Interrupt Handling when Programming/Erasing Flash Memory....................................... 716
23.10 Flash Memory Programmer Mode .................................................................................... 717
23.11 Flash Memory Programming and Erasing Precautions..................................................... 729
23.12 Note on Switching from F-ZTAT Version to Mask ROM Version .................................. 730
Section 24 Clock Pulse Generator
24.1 Overview........................................................................................................................... 731
24.2 Register Descriptions ........................................................................................................ 732
24.3 Oscillator........................................................................................................................... 734
24.4 Duty Adjustment Circuit................................................................................................... 739
24.5 Medium-Speed Clock Divider .......................................................................................... 739
24.6 Bus Master Clock Selection Circuit .................................................................................. 739
24.7 Subclock Input Circuit ...................................................................................................... 739
24.8 Subclock Waveform Shaping Circuit................................................................................ 740
24.9 Clock Selection Circuit ..................................................................................................... 741
Section 25 Power-Down State
25.1 Overview........................................................................................................................... 743
25.2 Register Descriptions ........................................................................................................ 747
Rev. 4.00 Sep 27, 2006 page xl of xliv
23.8.3 Error Protection.................................................................................................... 714
23.10.1 Programmer Mode Setting ................................................................................... 717
23.10.2 Socket Adapters and Memory Map ..................................................................... 718
23.10.3 Programmer Mode Operation .............................................................................. 718
23.10.4 Memory Read Mode ............................................................................................ 719
23.10.5 Auto-Program Mode ............................................................................................ 723
23.10.6 Auto-Erase Mode................................................................................................. 725
23.10.7 Status Read Mode ................................................................................................ 726
23.10.8 Status Polling ....................................................................................................... 727
23.10.9 Programmer Mode Transition Time .................................................................... 728
23.10.10 Notes on Memory Programming...................................................................... 729
24.1.1 Block Diagram ..................................................................................................... 731
24.1.2 Register Configuration......................................................................................... 732
24.2.1 Standby Control Register (SBYCR) .................................................................... 732
24.2.2 Low-Power Control Register (LPWRCR) ........................................................... 733
24.3.1 Connecting a Crystal Resonator........................................................................... 734
24.3.2 External Clock Input ............................................................................................ 736
25.1.1 Register Configuration......................................................................................... 747
25.2.1 Standby Control Register (SBYCR) .................................................................... 747
25.2.2 Low-Power Control Register (LPWRCR) ........................................................... 749
25.2.3 Timer Control/Status Register (TCSR) ................................................................ 751
25.2.4 Module Stop Control Register (MSTPCR) .......................................................... 752
......................................................................................... 743
.................................................................................. 731