DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 546

• Manufacturer Part Number: DF2148RTE20IV
• Description: MCU 5V 128K I-TEMP,PB-FREE, 100-
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148RTE20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 I
DDCSWR
Bit 6
SW
0
1
Note:
16.2.3
SARX is an 8-bit readable/writable register that stores the second slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device specified by the master device. SARX is assigned to the same
address as ICDR, and can be written and read only when the ICE bit is cleared to 0 in ICCR.
SARX is initialized to H'01 by a reset and in hardware standby mode.
Rev. 4.00 Sep 27, 2006 page 500 of 1130
REJ09B0327-0400
Bit
Initial value
Read/Write
* Do not set this mode when automatic switching to the I
Second Slave Address Register (SARX)
means of the DDCSWR setting.
SAR
Bit 0
FS
0
1
0
0
1
1
2
C Bus Interface [Option]
SVAX6
R/W
7
0
SARX
Bit 0
FSX
0
1
0
1
0
1
0
1
SVAX5
R/W
6
0
SVAX4
Operating Mode
I
I
I
Synchronous serial format
Formatless mode (start/stop conditions not detected)
Formatless mode * (start/stop conditions not detected)
2
2
2
R/W
C bus format
C bus format
C bus format
5
0
SAR and SARX slave addresses recognized
SAR slave address recognized
SARX slave address ignored
SAR slave address ignored
SARX slave address recognized
SAR and SARX slave addresses ignored
Acknowledge bit used
No acknowledge bit
SVAX3
R/W
4
0
SVAX2
R/W
3
0
2
C bus format is performed by
SVAX1
R/W
2
0
SVAX0
R/W
1
0
(Initial value)
FSX
R/W
0
1