DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 342

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 10 14-Bit PWM Timer (PWMX)
Bit 1—Carrier Frequency Select (CFS)
Bit 1
CFS
0
1
DADRA Bit 0—Reserved: This bit cannot be modified and is always read as 1.
DADRB Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS
bit can be accessed regardless of whether DADRB or DACNT is selected.
Bit 0
REGS
0
1
10.2.3
DACR is an 8-bit readable/writable register that selects test mode, enables the PWM outputs, and
selects the output phase and operating speed.
DACR is initialized to H'30 by a reset, and in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bit 7—Test Mode (TEST): Selects test mode, which is used in testing the chip. Normally this bit
should be cleared to 0.
Rev. 4.00 Sep 27, 2006 page 296 of 1130
REJ09B0327-0400
Bit
Initial value
Read/Write
PWM D/A Control Register (DACR)
Description
Base cycle = resolution (T)
DADR range = H'0401 to H'FFFD
Base cycle = resolution (T)
DADR range = H'0103 to H'FFFF
Description
DADRA and DADRB can be accessed
DACR and DACNT can be accessed
TEST
R/W
7
0
PWME
R/W
6
0
5
1
64
256
4
1
OEB
R/W
3
0
OEA
R/W
2
0
R/W
OS
1
0
(Initial value)
(Initial value)
CKS
R/W
0
0

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