DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 754

• Manufacturer Part Number: DF2148RTE20IV
• Description: MCU 5V 128K I-TEMP,PB-FREE, 100-
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148RTE20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 23 ROM
23.7
In the on-board programming modes, flash memory programming and erasing is performed by
software, using the CPU. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by
setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1.
The flash memory cannot be read while being programmed or erased. Therefore, the program that
controls flash memory programming/erasing (the programming control program) should be
located and executed in on-chip RAM or external memory.
Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, EV, PV, E, and P bits in
23.7.1
Follow the procedure shown in the program/program-verify flowchart in figure 23.12 to write data
or programs to flash memory. Performing program operations according to this flowchart will
enable data or programs to be written to flash memory without subjecting the device to voltage
stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a
time.
The wait times (x, y, z1, z2, z3, , ß,
memory control registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of writes (N),
see section 26.2.6, Flash Memory Characteristics.
Following the elapse of (x) µs or more after the SWE bit is set to 1 in flash memory control
register 1 (FLMCR1), 128-byte program data is stored in the program data area and reprogram
data area, and the 128-byte data in the reprogram data area written consecutively to the write
addresses. The lower 8 bits of the first address written to must be H'00 or H'80. 128 consecutive
byte data transfers are performed. The program address and program data are latched in the flash
memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this
case, H'FF data must be written to the extra addresses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.
Set a value greater than (y + z2 +
for program mode (program setup) is carried out by setting the PSU bit in FLMCR2, and after the
elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in
FLMCR1. The time during which the P bit is set is the flash memory programming time. Make a
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REJ09B0327-0400
2. Perform programming in the erased state. Do not perform additional programming on
Programming/Erasing Flash Memory
Program Mode
FLMCR1, and the ESU and PSU bits in FLMCR2, is executed by a program in flash
memory.
previously programmed addresses.
(H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
+ ) s as the WDT overflow period. After this, preparation
after setting/clearing individual bits in flash