DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 510

• Manufacturer Part Number: DF2148RTE20IV
• Description: MCU 5V 128K I-TEMP,PB-FREE, 100-
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148RTE20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 Serial Communication Interface (SCI, IrDA)
In serial reception, the SCI operates as described below.
1. The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal
2. The received data is stored in RSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
Note: * Subsequent receive operations cannot be performed when a receive error has occurred.
4. If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt
Rev. 4.00 Sep 27, 2006 page 464 of 1130
REJ09B0327-0400
synchronization and starts reception.
After receiving these bits, the SCI carries out the following checks.
a. Parity check:
b. Stop bit check:
c. Status check:
If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in
RDR.
If a receive error * is detected in the error check, the operation is as shown in table 15.11.
(RXI) request is generated.
Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a
receive-error interrupt (ERI) request is generated.
The SCI checks whether the number of 1 bits in the receive data agrees with the parity
(even or odd) set in the O/E bit in SMR.
The SCI checks whether the stop bit is 1.
If there are two stop bits, only the first is checked.
The SCI checks whether the RDRF flag is 0, indicating that the receive data can be
transferred from RSR to RDR.
Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be
cleared to 0.