DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 666

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 20 A/D Converter
20.2.3
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D
conversion operations.
ADCR is initialized to H'3F by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): These bits select enabling or
disabling of the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0
while conversion is stopped.
Bit 7
TRGS1
0
1
Bits 5 to 0—Reserved: Should always be written with 1.
Note: Some of these bits are readable/writable in products other than the HD64F2148,
Rev. 4.00 Sep 27, 2006 page 620 of 1130
REJ09B0327-0400
Bit
Initial value
Read/Write
HD64F2147N, HD64F2144, HD64F2142R and HD6432142, however, when writing, be
sure to write 1 here for software compatibility.
A/D Control Register (ADCR)
Bit 6
TRGS0
0
1
0
1
TRGS1
R/W
7
0
Description
Start of A/D conversion by external trigger is disabled
Start of A/D conversion by external trigger is disabled
Start of A/D conversion by external trigger (8-bit timer) is enabled
Start of A/D conversion by external trigger pin is enabled
TRGS0
R/W
6
0
5
1
4
1
3
1
2
1
1
1
(Initial value)
0
1

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