DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 1121

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
TCSRX—Timer Control/Status Register X
Note:
Bit
Initial value
Read/Write
TCSRX
Compare match flag B
0
1
* Only 0 can be written in bits 7 to 4, to clear the flags.
[Clearing conditions]
• When 0 is written in CMFB after reading CMFB = 1
• When the DTC is activated by a CMIB interrupt
[Setting condition]
When TCNT = TCORB
R/(W) *
CMFB
7
0
R/(W) *
CMFA
Compare match flag A
0
1
6
0
[Clearing conditions]
• When 0 is written in CMFA after reading CMFA = 1
• When the DTC is activated by a CMIA interrupt
[Setting condition]
When TCNT = TCORA
R/(W) *
Timer overflow flag
OVF
0
1
5
0
[Clearing condition]
When 0 is written in OVF after reading OVF = 1
[Setting condition]
When TCNT overflows from H'FF to H'00
Input capture flag
0
1
R/(W) *
[Clearing condition]
When 0 is written in ICF after reading ICF = 1
[Setting condition]
When a rising edge followed by a falling edge is
detected in the external reset signal after the
ICST bit in TCONRI has been set to 1
ICF
4
0
Output select 3 and 2
0
1
Rev. 4.00 Sep 27, 2006 page 1075 of 1130
Output select 1 and 0
OS3
R/W
H'FFF1
0
1
0
1
0
1
3
0
No change at compare match B
0 output at compare match B
1 output at compare match B
Output inverted at compare
match B (toggle output)
0
1
0
1
Appendix B Internal I/O Registers
OS2
R/W
No change at compare match A
0 output at compare match A
1 output at compare match A
Output inverted at compare
match A (toggle output)
2
0
OS1
R/W
1
0
REJ09B0327-0400
OS0
R/W
0
0
TMRX

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