DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 1109
![MCU 5V 128K I-TEMP,PB-FREE, 100-](/photos/28/61/286108/100-tqfp_sml.jpg)
DF2148RTE20IV
Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148RTE20IV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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TCR0—Timer Control Register 0
TCR1—Timer Control Register 1
TCRX—Timer Control Register X
TCRY—Timer Control Register Y
Compare Match Interrupt Enable B
0 CMFB interrupt request (CMIB) is disabled
1 CMFB interrupt request (CMIB) is enabled
Bit
Initial value
Read/Write
Compare match interrupt enable A
0 CMFA interrupt request (CMIA) is disabled
1 CMFA interrupt request (CMIA) is enabled
Timer overflow interrupt enable
0 OVF interrupt request (OVI) is disabled
1 OVF interrupt request (OVI) is enabled
CMIEB
Counter clear 1 and 0
0
1
R/W
7
0
0
1
0
1
Clear is disabled
Cleared on compare
match A
Cleared on compare
match B
Cleared on rising edge
of external reset input
CMIEA
R/W
6
0
OVIE
R/W
5
0
Notes: 1.
Channel
Clock select 2 to 0
CCLR1
All
X
Y
0
1
R/W
2.
4
0
Selected by ICKS1 and ICKS0 in STCR. For details, see section 12.2.4,
Timer Control Register (TCR).
If the clock input of channel 0 is the TCNT1 overflow signal and that of
channel 1 is the TCNT0 compare match signal, no incrementing clock is
generated. Do not use this setting.
CKS2
Bit 2
0
1
0
1
0
1
0
1
1
Rev. 4.00 Sep 27, 2006 page 1063 of 1130
CKS1 CKS0
Bit 1
CCLR0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
H'FFC8
H'FFC9
H'FFF0
H'FFF0
R/W
3
0
Bit 0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
1
0
1
*
*
*
*
*
*
1
1
1
1
1
1
Appendix B Internal I/O Registers
Clock input disabled
Internal clock: counting at falling edge of /8
Internal clock: counting at falling edge of /2
Internal clock: counting at falling edge of /64
Internal clock: counting at falling edge of /32
Internal clock: counting at falling edge of /1024
Internal clock: counting at falling edge of /256
Counting at TCNT1 overflow signal *
Clock input disabled
Internal clock: counting at falling edge of /8
Internal clock: counting at falling edge of /2
Internal clock: counting at falling edge of /64
Internal clock: counting at falling edge of /128
Internal clock: counting at falling edge of /1024
Internal clock: counting at falling edge of /2048
Count at TCNT0 compare match A *
Clock input disabled
Internal clock: counting on
Internal clock: counting at falling edge of /2
Internal clock: counting at falling edge of /4
Clock input disabled
Clock input disabled
Internal clock: counting at falling edge of /4
Internal clock: counting at falling edge of /256
Internal clock: counting at falling edge of /2048
Clock input disabled
External clock: counting at rising edge
External clock: counting at falling edge
External clock: counting at both rising and falling
edges
CKS2
R/W
2
0
CKS1
R/W
1
0
Description
REJ09B0327-0400
CKS0
R/W
0
0
2
2
TMRX
TMRY
TMR0
TMR1
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