DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 565

• Manufacturer Part Number: DF2148RTE20IV
• Description: MCU 5V 128K I-TEMP,PB-FREE, 100-
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148RTE20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 5—DDC Mode Switch Interrupt Enable Bit (IE): Enables or disables an interrupt request to
the CPU when automatic format switching is executed for IIC channel 0.
Bit 4—DDC Mode Switch Interrupt Flag (IF): Flag that indicates an interrupt request to the
CPU when automatic format switching is executed for IIC channel 0.
Bits 3 to 0—IIC Clear 3 to 0 (CLR3 to CLR0): These bits control initialization of the internal
state of IIC0 and IIC1.
These bits can only be written to; if read they will always return a value of 1.
When a write operation is performed on these bits, a clear signal is generated for the internal latch
circuit of the corresponding module(s), and the internal state of the IIC module(s) is initialized.
The write data for these bits is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be
written to simultaneously using an MOV instruction. Do not use a bit-manipulation instruction
such as BCLR.
When clearing is required again, all the bits must be written to in accordance with the setting.
Bit 5
IE
0
1
Bit 4
IF
0
1
Description
Interrupt when automatic format switching is executed is disabled
Interrupt when automatic format switching is executed is enabled
Description
No interrupt is requested when automatic format switching is executed
[Clearing condition]
When 0 is written in IF after reading IF = 1
An interrupt is requested when automatic format switching is executed
[setting condition]
When a falling edge is detected on the SCL pin when SWE = 1
Rev. 4.00 Sep 27, 2006 page 519 of 1130
Section 16 I
2
C Bus Interface [Option]
REJ09B0327-0400
(Initial value)
(Initial value)