DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 508

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 15 Serial Communication Interface (SCI, IrDA)
Serial Data Reception (Asynchronous Mode): Figure 15.7 shows a sample flowchart for serial
reception.
The following procedure should be used for serial data reception.
Rev. 4.00 Sep 27, 2006 page 462 of 1130
REJ09B0327-0400
No
No
Read receive data in RDR, and
clear RDRF flag in SSR to 0
PER
Clear RE bit in SCR to 0
Read RDRF flag in SSR
Read ORER, PER, and
Figure 15.7 Sample Serial Reception Data Flowchart
All data received?
FER flags in SSR
Start reception
Initialization
FER
RDRF = 1?
<End>
Yes
Yes
ORER = 1?
No
(Continued on next page)
Error handling
Yes
[1]
[2]
[4]
[5]
[3]
[1]
[2] [3]
[4]
[5]
SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
break detection:
If a receive error occurs, read the
ORER, PER, and FER flags in
SSR to identify the error. After
performing the appropriate error
handling, ensure that the ORER,
PER, and FER flags are all
cleared to 0. Reception cannot
be resumed if any of these flags
are set to 1. In the case of a
framing error, a break can be
detected by reading the value of
the input port corresponding to
the RxD pin.
SCI status check and receive
data read :
Read SSR and check that RDRF
= 1, then read the receive data in
RDR and clear the RDRF flag to
0. Transition of the RDRF flag
from 0 to 1 can also be identified
by an RXI interrupt.
Serial reception continuation
procedure:
To continue serial reception,
before the stop bit for the current
frame is received, read the
RDRF flag, read RDR, and clear
the RDRF flag to 0. The RDRF
flag is cleared automatically
when the DTC is activated by an
RXI interrupt and the RDR value
is read.
Receive error handling and

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