DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 791

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Notes: When a transition is made between modes by means of an interrupt, transition cannot be made
Program execution state
SLEEP instruction
SSBY = 1, PSS = 1,
DTON = 1, LSON = 0
Clock switching
exception handling
after oscillation
setting time
(STS2 to STS0)
on interrupt source generation alone. Ensure that interrupt handling is performed after accepting
the interrupt request.
From any state except hardware standby mode, a transition to the reset state occurs whenever
RES goes low.
From any state, a transition to hardware standby mode occurs when STBY goes low.
When a transition is made to watch mode or subactive mode, high-speed mode must be set.
1. NMI, IRQ0 to IRQ2, IRQ6, IRQ7, and WDT1 interrupts
2. NMI, IRQ0 to IRQ7, and WDT0 interrupts, WDT1 interrupt, TMR0 interrupt, TMR1 interrupt
3. All interrupts
4. NMI, IRQ0 to IRQ2, IRQ6, IRQ7
SCK2 to
SCK0
Subactive mode
Medium-speed
(main clock)
(main clock)
Reset state
High-speed
(subclock)
mode
0
mode
: Transition after exception handling
SCK2 to
SCK0
RES pin = high
SLEEP instruction
SSBY = 1, PSS = 1,
DTON = 1, LSON = 1
Clock switching
exception handling
Figure 25.1 Mode Transitions
0
STBY pin = high
RES pin = low
SLEEP instruction
Interrupt *
Any interrupt *
External
interrupt *
Interrupt *
LSON bit = 0
SLEEP
instruction
SLEEP
instruction
SLEEP
instruction
Interrupt *
LSON bit = 1
Rev. 4.00 Sep 27, 2006 page 745 of 1130
SLEEP
instruction
4
2
1
,
1
3
,
Section 25 Power-Down State
SSBY = 0, LSON = 0
Program-halted state
PSS = 1, DTON = 0
PSS = 0, LSON = 0
PSS = 1, LSON = 1
Subsleep mode
STBY pin = low
standby mode
standby mode
Watch mode
(main clock)
: Power-down mode
Sleep mode
(subclock)
(subclock)
Hardware
SSBY = 1
SSBY = 1
SSBY = 0
Software
REJ09B0327-0400

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