DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 365

• Manufacturer Part Number: DF2148RTE20IV
• Description: MCU 5V 128K I-TEMP,PB-FREE, 100-
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148RTE20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 1—Timer Overflow Flag (OVF): This status flag indicates that the FRC has overflowed
(changed from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware,
however, and cannot be set by software.
Bit 0—Counter Clear A (CCLRA): This bit selects whether the FRC is to be cleared at compare-
match A (when the FRC and OCRA values match).
11.2.8
TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture
signals, enables the input capture buffer mode, and selects the FRC clock source.
TCR is initialized to H'00 by a reset and in hardware standby mode
Bit 7—Input Edge Select A (IEDGA): Selects the rising or falling edge of the input capture A
signal (FTIA).
Bit 1
OVF
0
1
Bit 0
CCLRA
0
1
Bit
Initial value
Read/Write
Timer Control Register (TCR)
Description
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
[Setting condition]
When FRC changes from H'FFFF to H'0000
Description
FRC clearing is disabled
FRC is cleared at compare-match A
IEDGA
R/W
7
0
IEDGB
R/W
6
0
IEDGC
R/W
5
0
IEDGD
R/W
4
0
Rev. 4.00 Sep 27, 2006 page 319 of 1130
BUFEA
R/W
Section 11 16-Bit Free-Running Timer
3
0
BUFEB
R/W
2
0
CKS1
R/W
REJ09B0327-0400
1
0
(Initial value)
(Initial value)
CKS0
R/W
0
0