DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 319

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
8.12.2
Table 8.25 summarizes the port B registers.
Table 8.25 Port B Registers
Notes: 1. Lower 16 bits of the address.
Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port B. PBDDR has the same address as P7PIN, and if read, the port 7 pin states will be
returned.
Setting a PBDDR bit to 1 makes the corresponding port B pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Name
Port B data direction register
Port B output data register
Port B input data register
Bit
Initial value
Read/Write
Modes 1, 2 and 3 (EXPE = 1)
When the ABW bit in WSCR is cleared to 0, port B pins automatically become data I/O pins
(D7 to D0), regardless of the input/output direction indicated by PBDDR. When the ABW bit
is 1, a port B pin becomes an output port if the corresponding PBDDR bit is set to 1, and an
input port if the bit is cleared to 0.
Data I/O pins go to the high-impedance state after a reset, and in hardware standby mode or
software standby mode.
2. PBDDR has the same address as P7PIN.
3. PBPIN has the same address as P8DDR.
Register Configuration
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
W
7
0
W
6
0
Abbreviation
PBDDR
PBODR
PBPIN
W
5
0
W
4
0
R/W
W
R/W
R
Rev. 4.00 Sep 27, 2006 page 273 of 1130
W
3
0
Initial Value
H'00
H'00
Undefined
W
2
0
Section 8 I/O Ports
REJ09B0327-0400
W
1
0
Address *
H'FFBE *
H'FFBC
H'FFBD *
W
0
0
2
3
1

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