DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 205

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
6.3.4
In this LSI, an I/O select signal (IOS) can be output, with the signal output going low when the
designated external space is accessed.
Figure 6.2 shows an example of IOS signal output timing.
Enabling or disabling of IOS signal output is controlled by the setting of the IOSE bit in SYSCR.
In expanded mode, this pin operates as the AS output pin after a reset, and therefore the IOSE bit
in SYSCR must be set to 1 in order to use this pin as the IOS signal output. See section 8, I/O
Ports, for details.
The range of addresses for which the IOS signal is output can be set with bits IOS1 and IOS0 in
BCR. The IOS signal address ranges are shown in table 6.4.
Table 6.4
Note:
IOS1
0
1
Address bus
IOS
* In the H8S/2148 and H8S/2147 F-ZTAT A-mask version, the address range is from
I/O Select Signal
H'(FF)F000 to H'(FF)F7FF.
IOS
IOS Signal Output Range Settings
IOS
IOS
IOS0
0
1
0
1
Figure 6.2 IOS
IOS
IOS
IOS
IOS Signal Output Range
H'(FF)F000 to H'(FF)F03F
H'(FF)F000 to H'(FF)F0FF
H'(FF)F000 to H'(FF)F3FF
H'(FF)F000 to H'(FF)FE4F *
T
1
External address in IOS set range
IOS
IOS
IOS Signal Output Timing
Bus cycle
T
Rev. 4.00 Sep 27, 2006 page 159 of 1130
2
Section 6 Bus Controller
T
3
REJ09B0327-0400
(Initial value)

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