DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 644

• Manufacturer Part Number: DF2148RTE20IV
• Description: MCU 5V 128K I-TEMP,PB-FREE, 100-
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148RTE20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 Host Interface
this pin by sending commands and data. This function is available only when register IDR1 is
accessed using CS1. Slave logic decodes the commands input from the host processor. When an
H'D1 host command is detected, bit 1 of the data following the host command is output from the
GA20 output pin. This operation does not depend on firmware or interrupts, and is faster than the
regular processing using interrupts. Table 18.6 lists the conditions that set and clear GA20 (P81).
Figure 18.2 shows the GA20 output in flowchart form. Table 18.7 indicates the GA20 output
signal values.
Table 18.6 GA20 (P81) Set/Clear Timing
Pin Name
GA20
(P81)
Rev. 4.00 Sep 27, 2006 page 598 of 1130
REJ09B0327-0400
Setting Condition
Rising edge of the host’s write signal
(IOW) when bit 1 of the written data is 1
and the data follows an H'D1 host
command
No
No
Figure 18.2 GA20 Output
Write bit 1 of data byte
to DR bit of P81/GA20
Wait for next byte
H'D1 command
Data byte?
received?
Start
Yes
Yes
Host write
Host write
Clearing Condition
Rising edge of the host’s write signal
(IOW) when bit 1 of the written data is 0
and the data follows an H'D1 host
command
Also, when bit FGA20E in HICR is cleared
to 0