DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 620

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 574 of 1130
REJ09B0327-0400
Disable receive abort
RXCR3 to RXCR0
Read KBCRH
Receive state
Read KBCRL
KBF = 0?
requests
B'1001?
Start
Yes
Yes
Figure 17.7 Sample Receive Abort Processing Flowchart
[3]
No
No
and clear receive counter)
(disable KBBR reception
(receive abort request)
command transmission
To transmit operation
Clear I/O inhibit
Transmit data
(KCLKO = 1)
Processing 1
KCLKO = 0
Set start bit
(KDO = 0)
Retransmit
KBE = 0
(data)?
Yes
[1]
[2]
No
[1] Read KBCRL, and if KBF = 1,
[2] Read KBCRH, and if the value of
[3] If the value of bits RXCR3 to
perform processing 1.
bits RXCR3 to RXCR0 is less than
B'1001, write 0 in KCLKO to abort
reception.
If the value of bits RXCR3 to
RXCR0 is B'1001 or greater, wait
until stop bit reception is
completed, then perform receive
data processing, and proceed to
the next operation.
RXCR0 is B'1001 or greater, the
parity bit is being received. With
the PS2 interface, a receive abort
request following parity bit
reception is disabled. Wait until
stop bit reception is completed,
perform receive data processing
and clear the KBF flag, then
proceed to the next operation.
and clear receive counter)
(disable KBBR reception
(enable KB operation)
To receive operation
Clear I/O inhibit
(KCLKO = 1)
KBE = 0
KBE = 1

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