DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 428

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 13 Timer Connection
Bits 3 to 0—Input Synchronization Signal Inversion (HFINV, VFINV, HIINV, VIINV):
These bits select inversion of the input phase of the spare horizontal synchronization signal
(HFBACKI), the spare vertical synchronization signal (VFBACKI), the horizontal
synchronization signal and composite synchronization signal (HSYNCI, CSYNCI), and the
vertical synchronization signal (VSYNCI).
Bit 3
HFINV
0
1
Bit 2
VFINV
0
1
Bit 1
HIINV
0
1
Bit 0
VIINV
0
1
Rev. 4.00 Sep 27, 2006 page 382 of 1130
REJ09B0327-0400
Description
The HFBACKI pin state is used directly as the HFBACKI input
The HFBACKI pin state is inverted before use as the HFBACKI input
Description
The VFBACKI pin state is used directly as the VFBACKI input
The VFBACKI pin state is inverted before use as the VFBACKI input
Description
The HSYNCI and CSYNCI pin states are used directly as the HSYNCI
and CSYNCI inputs
The HSYNCI and CSYNCI pin states are inverted before use as the HSYNCI and
CSYNCI inputs
Description
The VSYNCI pin state is used directly as the VSYNCI input
The VSYNCI pin state is inverted before use as the VSYNCI input
(Initial value)
(Initial value)
(Initial value)
(Initial value)

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