DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 186

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 5 Interrupt Controller
5.5.3
Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts
by means of the I and UI bits in the CPU’s CCR, and ICR.
For example, if the interrupt enable bit for an interrupt request is set to 1, and H'20, H'00, and H'00
are set in ICRA, ICRB, and ICRC, respectively, (i.e. IRQ2 and IRQ3 interrupts are set to control
level 1 and other interrupts to control level 0), the situation is as follows:
Figure 5.9 shows the state transitions in these cases.
Rev. 4.00 Sep 27, 2006 page 140 of 1130
REJ09B0327-0400
Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled when
set to 1.
Control level 1 interrupt requests are enabled when the I bit or UI bit is cleared to 0, and
disabled when both the I bit and the UI bit are set to 1.
When I = 0, all interrupts are enabled
(Priority order: NMI > IRQ2 > IRQ3 > address break > IRQ0 > IRQ1 ...)
When I = 1 and UI = 0, only NMI, IRQ2, IRQ3 and address break interrupts are enabled
When I = 1 and UI = 1, only NMI and address break interrupts are enabled
Exception handling execution
All interrupts enabled
Interrupt Control Mode 1
or I
Figure 5.9 Example of State Transitions in Interrupt Control Mode 1
1, UI
1
I
0
Only NMI interrupts and
address break enabled
I
I
1, UI
0
0
UI
0
Exception handling execution
Only NMI, IRQ2, IRQ3,
and address break
interrupts enabled
or UI
1

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