DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 636

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 18 Host Interface
18.2.3
HICR is an 8-bit readable/writable register which controls host interface channel 1 and 2 interrupts
and the fast A20 gate function. HICR2 is an 8-bit readable/writable register which controls host
interface channel 3 and 4 interrupts. HICR and HICR2 are initialized to H'F8 by a reset and in
hardware standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.
HICR Bits 2 and 1—Input Data Register Full Interrupt Enable 2 and 1 (IBFIE2, IBFIE1)
HICR2 Bits 2 and 1—Input Data Register Full Interrupt Enable 4 and 3 (IBFIE4, IBFIE3)
These bits enable or disable the IBF1, IBF2, IBF3, and IBF4 interrupts to the internal CPU.
Rev. 4.00 Sep 27, 2006 page 590 of 1130
REJ09B0327-0400
Bit
Initial value
Slave Read/Write
Host Read/Write
Bit
Initial value
Slave Read/Write
Host Read/Write
HICR
HICR2
Host Interface Control Register (HICR)
7
1
7
1
6
1
6
1
5
1
5
1
4
1
4
1
3
1
3
1
IBFIE2
IBFIE4
R/W
R/W
2
0
2
0
IBFIE1
IBFIE3
R/W
R/W
1
0
1
0
FGA20E
R/W
0
0
0
0

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