DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 217

• Manufacturer Part Number: DF2148RTE20IV
• Description: MCU 5V 128K I-TEMP,PB-FREE, 100-
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148RTE20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller
6.4.5
Wait Control
When accessing external space, the MCU can extend the bus cycle by inserting one or more wait
states (T
). There are three ways of inserting wait states: program wait insertion, pin wait insertion
W
using the WAIT pin, and a combination of the two.
Program Wait Mode: In program wait mode, the number of T
states specified by bits WC1 and
W
WC0 are always inserted between the T
and T
states when external space is accessed.
2
3
Pin Wait Mode: In pin wait mode, the number of T
states specified by bits WC1 and WC0 are
W
states when external space is accessed. If the WAIT pin is
always inserted between the T
and T
2
3
state is inserted. If the WAIT pin is held
low at the fall of in the last T
or T
state, another T
2
W
W
low, T
states are inserted until it goes high.
W
Pin wait mode is useful for inserting four or more wait states, or for changing the number of T
W
states for different external devices.
Pin Auto-Wait Mode: In pin auto-wait mode, if the WAIT pin is low at the fall of in the T
2
state, the number of T
states specified by bits WC1 and WC0 are inserted when external space is
W
states are inserted even if the WAIT pin remains low. Pin auto-wait
accessed. No additional T
W
mode can be used for an easy interface to low-speed memory, simply by routing the chip select
signal to the WAIT pin.
Figure 6.13 shows an example of wait state insertion timing.
Rev. 4.00 Sep 27, 2006 page 171 of 1130
REJ09B0327-0400