DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 31

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
7.3
7.4
7.5
Section 8 I/O Ports
8.1
8.2
8.3
8.4
8.5
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
Operation .......................................................................................................................... 189
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10 Number of DTC Execution States........................................................................ 202
7.3.11 Procedures for Using the DTC............................................................................. 204
7.3.12 Examples of Use of the DTC ............................................................................... 205
Interrupts ........................................................................................................................... 207
Usage Notes ...................................................................................................................... 207
Overview........................................................................................................................... 209
Port 1................................................................................................................................. 221
8.2.1
8.2.2
8.2.3
8.2.4
Port 2................................................................................................................................. 226
8.3.1
8.3.2
8.3.3
8.3.4
Port 3................................................................................................................................. 233
8.4.1
8.4.2
8.4.3
8.4.4
Port 4................................................................................................................................. 238
8.5.1
DTC Destination Address Register (DAR).......................................................... 185
DTC Transfer Count Register A (CRA) .............................................................. 186
DTC Transfer Count Register B (CRB)............................................................... 186
DTC Enable Registers (DTCER) ......................................................................... 187
DTC Vector Register (DTVECR)........................................................................ 188
Module Stop Control Register (MSTPCR) .......................................................... 189
Overview.............................................................................................................. 189
Activation Sources ............................................................................................... 191
DTC Vector Table................................................................................................ 193
Location of Register Information in Address Space ............................................ 195
Normal Mode....................................................................................................... 196
Repeat Mode ........................................................................................................ 197
Block Transfer Mode ........................................................................................... 198
Chain Transfer ..................................................................................................... 200
Operation Timing................................................................................................. 201
Overview.............................................................................................................. 221
Register Configuration......................................................................................... 222
Pin Functions in Each Mode ................................................................................ 224
MOS Input Pull-Up Function............................................................................... 226
Overview.............................................................................................................. 226
Register Configuration......................................................................................... 228
Pin Functions in Each Mode ................................................................................ 230
MOS Input Pull-Up Function............................................................................... 232
Overview.............................................................................................................. 233
Register Configuration......................................................................................... 234
Pin Functions in Each Mode ................................................................................ 236
MOS Input Pull-Up Function............................................................................... 237
Overview.............................................................................................................. 238
.............................................................................................................. 209
Rev. 4.00 Sep 27, 2006 page xxix of xliv

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