DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 1034

• Manufacturer Part Number: DF2148RTE20IV
• Description: MCU 5V 128K I-TEMP,PB-FREE, 100-
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148RTE20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Appendix A Instruction Set
SLEEP
STC CCR,Rd
STC EXR,Rd
STC CCR,@ERd
STC EXR,@ERd
STC CCR,
@(d:16,ERd)
STC EXR,
@(d:16,ERd)
STC CCR,
@(d:32,ERd)
STC EXR,
@(d:32,ERd)
STC CCR,@-ERd
STC EXR,@-ERd
STC CCR,@aa:16
STC EXR,@aa:16
STC CCR,@aa:32
STC EXR,@aa:32
STM.L
(ERn-ERn+1),
@-SP *
STM.L
(ERn-ERn+2),
@-SP *
STM.L
(ERn-ERn+3),
@-SP *
STMAC MACH,ERd Cannot be used in this LSI
STMAC MACL,ERd
SUB.B Rs,Rd
SUB.W #xx:16,Rd
SUB.W Rs,Rd
SUB.L #xx:32,ERd R:W 2nd
SUB.L ERs,ERd
Rev. 4.00 Sep 27, 2006 page 988 of 1130
REJ09B0327-0400
Instruction
9
9
9
R:W NEXT Internal
R:W NEXT
R:W NEXT
R:W 2nd
R:W 2nd
R:W 2nd
R:W 2nd
R:W 2nd
R:W 2nd
R:W 2nd
R:W 2nd
R:W 2nd
R:W 2nd
R:W 2nd
R:W 2nd
R:W 2nd
R:W 2nd
R:W 2nd
R:W NEXT
R:W 2nd
R:W NEXT
R:W NEXT
1
operation
:M
R:W NEXT W:W EA
R:W NEXT W:W EA
R:W 3rd
R:W 3rd
R:W 3rd
R:W 3rd
R:W NEXT Internal
R:W NEXT Internal
R:W 3rd
R:W 3rd
R:W 3rd
R:W 3rd
R:W:M
NEXT
R:W:M
NEXT
R:W:M
NEXT
R:W NEXT
R:W 3rd
2
R:W NEXT W:W EA
R:W NEXT W:W EA
R:W 4th
R:W 4th
operation,
1 state
operation,
1 state
R:W NEXT W:W EA
R:W NEXT W:W EA
R:W 4th
R:W 4th
Internal
operation,
1 state
Internal
operation,
1 state
Internal
operation,
1 state
R:W NEXT
3
R:W 5th
R:W 5th
W:W EA
W:W EA
W:W:M
Stack (H)
*
W:W:M
Stack (H)
*
W:W:M
Stack (H)
*
R:W NEXT W:W EA
R:W NEXT W:W EA
3
3
3
4
R:W NEXT W:W EA
R:W NEXT W:W EA
W:W
Stack (L)
*
W:W
Stack (L)
*
W:W
Stack (L)
*
3
3
3
5
6
7
8
9