DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 465

Manufacturer Part Number

DF2148RTE20IV

MCU 5V 128K I-TEMP,PB-FREE, 100-

Manufacturer

Renesas Electronics America

H8® H8S/2100r

Core Processor

Connectivity

Host Interface, I²C, IrDA, SCI

POR, PWM, WDT

Number Of I /o

Program Memory Size

128KB (128K x 8)

Program Memory Type

Voltage - Supply (vcc/vdd)

Data Converters

A/D 8x10b; D/A 2x8b

Oscillator Type

Operating Temperature

-40°C ~ 85°C

Package / Case

100-TQFP, 100-VQFP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

When TCNT overflows in watchdog timer mode, the OVF bit is set to 1 in TCSR. If the RST/NMI

bit is 1 at this time, an internal reset signal is generated for the entire chip, and at the same time a

low-level signal is output from the RESO pin. The timing is shown in figure 14.6.

During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).

The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be

cleared to 0 in the interrupt handling routine. When NMI interrupt request generation is selected in

watchdog timer mode, an overflow generates an NMI interrupt request.

Overflow signal

(internal signal)

Internal reset

RESO Signal Output Timing

Figure 14.6 RESO

RESO Signal Output Timing

Rev. 4.00 Sep 27, 2006 page 419 of 1130

Section 14 Watchdog Timer (WDT)

REJ09B0327-0400