DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 611

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Bit 1—Parity Error (PER): Indicates that an odd parity error has occurred.
Bit 1
PER
0
1
Bit 0—Keyboard Stop (KBS): Indicates the receive data stop bit. Valid only when KBF = 1.
Bit 0
KBS
0
1
17.2.2
KBCRL is an 8-bit readable/writable register that enables the receive counter count and controls
the keyboard buffer controller pin output.
KBCRL is initialized to H'70 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bit 7—Keyboard Enable (KBE): Enables or disables loading of receive data into the keyboard
data buffer register (KBBR).
Bit 7
KBE
0
1
Bit
Initial value
Read/Write
Keyboard Control Register L (KBCRL)
[Clearing condition]
Read PER when PER =1, then write 0 in PER
[Setting condition]
When an odd parity error occurs
Description
0 stop bit received
1 stop bit received
Description
Loading of receive data into KBBR is disabled
Loading of receive data into KBBR is enabled
Description
KBE
R/W
7
0
KCLKO
R/W
6
1
KDO
R/W
5
1
4
1
Rev. 4.00 Sep 27, 2006 page 565 of 1130
RXCR3 RXCR2 RXCR1 RXCR0
Section 17 Keyboard Buffer Controller
R
3
0
R
2
0
REJ09B0327-0400
R
1
0
(Initial value)
(Initial value)
(Initial value)
R
0
0

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