DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 479

• Manufacturer Part Number: DF2148RTE20IV
• Description: MCU 5V 128K I-TEMP,PB-FREE, 100-
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148RTE20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.2.6
SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output
in asynchronous mode, and interrupt requests, and selection of the serial clock source.
SCR can be read or written to by the CPU at all times.
SCR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt
(TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE
flag in SSR is set to 1.
Note:
Bit 1
CKS1
0
1
Bit 7
TIE
0
1
Bit
Initial value
Read/Write
* TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag,
Serial Control Register (SCR)
then clearing it to 0, or clearing the TIE bit to 0.
Bit 0
CKS0
0
1
0
1
Description
Transmit-data-empty interrupt (TXI) request disabled *
Transmit-data-empty interrupt (TXI) request enabled
R/W
TIE
7
0
Description
/4 clock
/16 clock
/64 clock
clock
R/W
RIE
6
0
R/W
TE
5
0
Section 15 Serial Communication Interface (SCI, IrDA)
R/W
RE
4
0
Rev. 4.00 Sep 27, 2006 page 433 of 1130
MPIE
R/W
3
0
TEIE
R/W
2
0
CKE1
R/W
REJ09B0327-0400
1
0
(Initial value)
(Initial value)
CKE0
R/W
0
0