DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 1105

• Manufacturer Part Number: DF2148RTE20IV
• Description: MCU 5V 128K I-TEMP,PB-FREE, 100-
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148RTE20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

SYSCR—System Control Register
Bit
Initial value
Read/Write
CS2 enable
SYSCR
CS2E
Bit 7
0
1
IOS enable
Note: * In the H8S/2148 F-ZTAT A-mask version and H8S/2147 F-ZTAT A-mask version,
FGA20E
0
1
HICR
Bit 0
CS2E
R/W
0
1
0
1
The AS/IOS pin functions as the address strobe pin
(Low output when accessing an external area)
The AS/IOS pin functions as the I/O strobe pin
(Low output when accessing a specified address from H'(FF)F000 to H'(FF)FE4F) *
7
0
the address range is from H'(FF)F000 to H'(FF)F7FF.
CS2 pin function halted
(CS2 fixed high internally)
CS2 pin function selected for P81/CS2 pin
CS2 pin function selected for P90/ECS2 pin
Interrupt control mode select
INTM1
IOSE
0
R/W
6
0
INTM0
0
1
Description
INTM1
R
5
0
Interrupt control mode 0
Interrupt control mode 1
External reset
0
1
Description
NMI edge select
Reset generated by watchdog timer overflow
Reset generated by an external reset
0
1
INTM0
R/W
4
0
Falling edge
Rising edge
Rev. 4.00 Sep 27, 2006 page 1059 of 1130
XRST
H'FFC4
R
3
1
Host interface enable
0
1
Appendix B Internal I/O Registers
NMIEG
Addresses H'(FF)FFF0 to H'(FF)FFF7
and H'(FF)FFFC to H'(FF)FFFF are
used for access to 8-bit timer (channel
X and Y) data registers and control
registers, and timer connection
control registers
Addresses H'(FF)FFF0 to H'(FF)FFF7
and H'(FF)FFFC to H'(FF)FFFF are
used for access to host interface data
registers and control registers, and
keyboard controller and MOS input
pull-up control registers
R/W
2
0
RAM Enable
0
1
On-chip RAM is disabled
On-chip RAM is enabled
R/W
HIE
1
0
REJ09B0327-0400
RAME
R/W
0
1
System