DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 704

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 22 ROM
Automatic SCI Bit Rate Adjustment
When boot mode is initiated, this group MCU measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no parity. The MCU calculates the bit rate of
the transmission from the host from the measured low period, and transmits one H'00 byte to the
host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end
indication (H'00) has been received normally, and transmit one H'55 byte to the MCU. If reception
cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.
Depending on the host’s transmission bit rate and the MCU’s system clock frequency, there will
be a discrepancy between the bit rates of the host and the MCU. To ensure correct SCI operation,
the host’s transfer bit rate should be set to (2400, 4800, or 9600) bps.
Table 22.7 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of the MCU’s bit rate is possible. The boot program should be executed within this
system clock range.
Table 22.7 System Clock Frequencies for which Automatic Adjustment of This Group Bit
Host Bit Rate
9600 bps
4800 bps
2400 bps
Rev. 4.00 Sep 27, 2006 page 658 of 1130
REJ09B0327-0400
Figure 22.9 RxD1 Input Signal when Using Automatic SCI Bit Rate Adjustment
Rate Is Possible
(Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Start
bit
D0
System Clock Frequency for which Automatic Adjustment
of This Group Bit Rate Is Possible
8 MHz to 20 MHz
4 MHz to 20 MHz
2 MHz to 18 MHz
Low period (9 bits) measured (H'00 data)
D1
D2
D3
D4
D5
D6
D7
(1 or more bits)
High period
Stop
bit

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