DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 367

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Bit 2—Buffer Enable B (BUFEB): Selects whether ICRD is to be used as a buffer register for
ICRB.
Bits 1 and 0—Clock Select (CKS1, CKS0): Select external clock input or one of three internal
clock sources for the FRC. External clock pulses are counted on the rising edge of signals input to
the external clock input pin (FTCI).
11.2.9
TOCR is an 8-bit readable/writable register that enables output from the output compare pins,
selects the output levels, switches access between output compare registers A and B, controls the
ICRD and OCRA operating mode, and switches access to input capture registers A, B, and C.
TOCR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Input Capture D Mode Select (ICRDMS): Specifies whether ICRD is used in the normal
operating mode or in the operating mode using OCRDM.
Bit 2
BUFEB
0
1
Bit 1
CKS1
0
1
Bit
Initial value
Read/Write
Timer Output Compare Control Register (TOCR)
Description
ICRD is not used as a buffer register for input capture B
ICRD is used as a buffer register for input capture B
Bit 0
CKS0
0
1
0
1
ICRDMS
R/W
7
0
Description
External clock source (rising edge)
OCRAMS
/2 internal clock source
/8 internal clock source
/32 internal clock source
R/W
6
0
ICRS
R/W
5
0
OCRS
R/W
4
0
Rev. 4.00 Sep 27, 2006 page 321 of 1130
OEA
R/W
Section 11 16-Bit Free-Running Timer
3
0
OEB
R/W
2
0
OLVLA
R/W
REJ09B0327-0400
1
0
(Initial value)
(Initial value)
OLVLB
R/W
0
0

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