DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 460

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 14 Watchdog Timer (WDT)
Bit 4
PSS
0
1
Note:
14.2.3
Only bit 3 is described here. For details on functions not related to the watchdog timer, see
sections 3.2.2 and 5.2.1, System Control Register (SYSCR), and the descriptions of the relevant
modules.
Bit 3—External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a
reset can be generated by watchdog timer overflow in addition to external reset input. XRST is a
Rev. 4.00 Sep 27, 2006 page 414 of 1130
REJ09B0327-0400
Bit
Initial value
Read/Write
WDT1 input clock selection
* The overflow period is the time from when TCNT starts counting up from H'00 until
System Control Register (SYSCR)
Bit 2
CKS2
0
1
0
1
overflow occurs.
CS2E
R/W
Bit 1
CKS1
0
1
0
1
0
1
0
1
7
0
IOSE
R/W
Bit 0
CKS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
6
0
INTM1
R
5
0
Clock
/2 (Initial value) 25.6 µs
/64
/128
/512
/2048
/8192
/32768
/131072
SUB/2
SUB/4
SUB/8
SUB/16
SUB/32
SUB/64
SUB/128
SUB/256
INTM0
R/W
4
0
XRST
Overflow Period * (when
and
819.2 µs
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
15.6 ms
31.3 ms
62.5 ms
125 ms
250 ms
500 ms
1 s
2 s
R
3
1
Description
SUB
NMIEG
= 32.768 kHz)
R/W
2
0
R/W
HIE
1
0
= 20 MHz
RAME
R/W
0
1

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