DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 348

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 10 14-Bit PWM Timer (PWMX)
10.4
A PWM waveform like the one shown in figure 10.3 is output from the PWMX pin. When OS =
0, the value in DADR corresponds to the total width (T
conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 1, the output
waveform is inverted and the DADR value corresponds to the total width (T
output pulses. Figure 10.4 shows the types of waveform output available.
Table 10.4 summarizes the relationships of the CKS, CFS, and OS bit settings to the resolution,
base cycle, and conversion cycle. The PWM output remains flat unless DADR contains at least a
certain minimum value. Table 10.4 indicates the range of DADR settings that give an output
waveform like the one in figure 10.3, and lists the conversion cycle length when low-order DADR
bits are kept cleared to 0, reducing the conversion precision to 12 bits or 10 bits.
Rev. 4.00 Sep 27, 2006 page 302 of 1130
REJ09B0327-0400
Legend:
T: Resolution
T
(When CFS = 0, m = 256; when CFS = 1, m = 64)
L
=
Basic cycle
(T
n = 1
m
Operation
t
t
Ln
L
64 or T
t
f
(when OS = 0)
256)
Figure 10.3 PWM D/A Operation
(T
1 conversion cycle
2
14
(= 16384))
L
) of the low (0) pulses output in one
H
) of the high (1)

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