DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 170

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 5 Interrupt Controller
If any of bits KMIMR15 to KMIMR8 is cleared to 0, interrupt input from the IRQ7 pin will be
ignored. When pins KIN7 to KIN0 or KIN15 to KIN8 are used as key-sense interrupt input pins,
either low-level sensing or falling-edge sensing must be designated as the interrupt sense condition
for the corresponding interrupt source (IRQ6 or IRQ7).
5.2.8
ABRKCR is an 8-bit readable/writable register that performs address break control.
ABRKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Condition Match Flag (CMF): This is the address break source flag, used to indicate that
the address set by BAR has been prefetched. When the CMF flag and BIE flag are both set to 1, an
address break is requested.
Bit 7
CMF
0
1
Bits 6 to 1—Reserved: These bits cannot be modified and are always read as 0.
Bit 0—Break Interrupt Enable (BIE): Selects address break enabling or disabling.
Bit 0
BIE
0
1
Rev. 4.00 Sep 27, 2006 page 124 of 1130
REJ09B0327-0400
Bit
Initial value
Read/Write
Address Break Control Register (ABRKCR)
Description
[Clearing condition]
When address break interrupt exception handling is executed
[Setting condition]
When address set by BARA to BARC is prefetched while BIE = 1
Description
Address break disabled
Address break enabled
CMF
R
7
0
6
0
5
0
4
0
3
0
2
0
1
0
(Initial value)
(Initial value)
R/W
BIE
0
0

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