DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 640

• Manufacturer Part Number: DF2148RTE20IV
• Description: MCU 5V 128K I-TEMP,PB-FREE, 100-
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148RTE20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 Host Interface
Bit 0—Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR1. Cleared to
0 when the host processor reads ODR.
Bit 0
OBF
0
1
Table 18.3 shows the conditions for setting and clearing the STR flags.
Table 18.3 Set/Clear Timing for STR Flags
Flag
C/D
IBF *
OBF
Note:
Rev. 4.00 Sep 27, 2006 page 594 of 1130
REJ09B0327-0400
* The IBF flag setting and clearing conditions are different when the fast A20 gate is
used. For details see table 18.7.
Description
[Clearing condition]
When the host processor reads ODR or the slave writes 0 in the OBF bit (Initial value)
[Setting condition]
When the slave processor writes to ODR
Setting Condition
Rising edge of host’s write signal
(IOW) when HA0 is high
Rising edge of host’s write signal
(IOW) when writing to IDR1
Falling edge of slave’s internal write
signal (WR) when writing to ODR1
Clearing Condition
Rising edge of host’s write signal (IOW) when
HA0 is low
Falling edge of slave’s internal read signal (RD)
when reading IDR1
Rising edge of host’s read signal (IOR) when
reading ODR1