DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 187

• Manufacturer Part Number: DF2148RTE20IV
• Description: MCU 5V 128K I-TEMP,PB-FREE, 100-
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148RTE20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 5.10 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
2. When interrupt requests are sent to the interrupt controller, a control level 1 interrupt,
3. The I bit is then referenced. If the I bit is cleared to 0, the UI bit has no effect.
4. When an interrupt request is accepted, interrupt exception handling starts after execution of the
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
6. Next, the I and UI bits in CCR are set to 1. This disables all interrupts except NMI and address
7. A vector address is generated for the accepted interrupt, and execution of the interrupt
interrupt request is sent to the interrupt controller.
according to the control level set in ICR, has priority for selection, and other interrupt requests
are held pending. If a number of interrupt requests with the same control level setting are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in table 5.4 is selected.
An interrupt request set to interrupt control level 0 is accepted when the I bit is cleared to 0. If
the I bit is set to 1, only an NMI and address break interrupts are accepted, and other interrupt
requests are held pending.
An interrupt request set to interrupt control level 1 has priority over an interrupt request set to
interrupt control level 0, and is accepted if the I bit is cleared to 0, or if the I bit is set to 1 and
the UI bit is cleared to 0.
When both the I bit and the UI bit are set to 1, only an NMI and address break interrupts are
accepted, and other interrupt requests are held pending.
current instruction has been completed.
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
break.
handling routine starts at the address indicated by the contents of that vector address.
Rev. 4.00 Sep 27, 2006 page 141 of 1130
Section 5 Interrupt Controller
REJ09B0327-0400