MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 157

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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floating-point value does so using the double-precision floating-point format. Therefore, all floating-point
numbers are stored in double-precision format.
All floating-point arithmetic instructions operate on data located in FPRs and, with the exception of the
compare instructions (which update the CR), place the result into an FPR. Information about the status of
floating-point operations is placed into the floating-point status and control register (FPSCR) and in some
cases, after the completion of the operation’s writeback stage, into the CR. For information on how the CR
is affected by floating-point operations, see
3.7.3
The FPSCR controls the handling of floating-point exceptions and records status resulting from the
floating-point operations. FPSCR[0:23] are status bits. FPSCR[24:31] are control bits.
FPSCR[0:12] and FPSCR[21:23] are floating-point exception condition bits. These bits are sticky, except
for the floating-point enabled exception summary (FEX) and floating-point invalid operation exception
summary (VX). Once set, sticky bits remain set until they are cleared by an mcrfs, mtfsfi, mtfsf, or mtfsb0
instruction.
Table 3-4
which are control bits.
FEX and VX are the logical ORs of other FPSCR bits. Therefore these two bits are not listed among the
FPSCR bits directly affected by the various instructions.
Freescale Semiconductor
Reset
summarizes which bits in the FPSCR are sticky status bits, which are normal status bits, and
Floating-Point Status and Control Register (FPSCR)
MSB
0
[0], [3:12], [21:23]
Figure 3-5. Floating-Point Registers (FPRs)
[1:2], [13:20]
MPC561/MPC563 Reference Manual, Rev. 1.2
[24:31]
Bits
Table 3-4. FPSCR Bit Categories
Section 3.7.4, “Condition Register
Status, not sticky
Control
Status, sticky
Unchanged
FPR31
FPR0
FPR1
. . .
. . .
Type
(CR).”
Central Processing Unit
LSB
63
3-13

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