MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 797

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

When an event occurs in a submodule that activates a flag line, the corresponding flag bit in the status
register is set. The status register is read/write, but a flag bit can be reset only if it has previously been read
as a one. Writing a “one” to a flag bit has no effect. When the software intends to clear only one flag bit
within a status register, the software must write an all-ones 16-bit value except for the bit position to be
cleared which is a zero.
The enable register is initialized by the software to indicate whether each interrupt request is enabled for
the levels defined in the ICS.
Each bit in the IRQ pending register is the result of a logical “AND” between the corresponding bits in the
status and in the enable registers. If a flag bit is set and the level enable bit is also set, then the IRQ pending
bit is set, and the information is transferred to the interrupt control section that is in charge of sending the
corresponding level to the CPU. The IRQ pending register is read only.
The submodule number of an interrupting source defines the corresponding MIRSM number and the bit
position in the status registers. To find the MIRSM number and bit position of an interrupting source,
proceed as follow:
17.12.3 MIRSM0 Interrupt Registers
17.12.3.1 Interrupt Status Register (MIOS14SR0)
This register contains the flag bits that are raised when the submodules generate an interrupt. Each bit
corresponds to a given submodule.
Freescale Semiconductor
1. Divide the interrupting submodule number by 16
2. The integer result of the division gives the MIRSM number
3. The reminder of the division gives the bit position
If a submodule in a group of 16 cannot generate interrupts, then its
corresponding flag bit in the status register is inactive and is read as zero.
In the case of multiple requests levels implementation in the same MIOS14,
it is possible to enable interrupts at more than one different levels for the
same submodule. It is the responsibility of the software to manage this.
When the enable bit is not set for a particular submodule, the corresponding
status register bit is still set when the corresponding flag is set. This allows
the traditional software approach of polling the flag bits to see which ones
are set. The status register makes flag polling easy, since up to 16 flag bits
are contained in one register.
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
NOTE
NOTE
Modular Input/Output Subsystem (MIOS14)
17-65