MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 278
MPC562MZP56
Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC562MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
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Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
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System Configuration and Protection
6.2.2.3.2
The SWSR is the location to which the SWT servicing sequence is written. To prevent SWT time-out, a
0x556C followed by 0xAA39 should be written to this register. The SWSR can be written at any time but
returns all zeros when read.
6-38
HRESET
HRESET
16:23
25:27
Bits
0:15
24
28
29
30
31
Field
Addr
Field
MSB
SWTC
Name
SWRI
SWE
SWP
16
BME
SWF
BMT
Software Service Register (SWSR)
0
—
17
1
Software watchdog timer count. This field contains the count value of the software watchdog
timer.
Bus monitor timing. This field specifies the time-out period, in eight-system-clock resolution, of
the bus monitor. BMT must be set to non zero even if the bus monitor is not enabled.
Bus monitor enable
0 Disable bus monitor
1 Enable bus monitor
Reserved
Software watchdog freeze
0 Software watchdog continues to run while FREEZE is asserted
1 Software watchdog stops while FREEZE is asserted
Software watchdog enable. Software should clear this bit after a system reset to disable the
software watchdog timer.
0 Watchdog is disabled
1 Watchdog is enabled
Software watchdog reset/interrupt select
0 Software watchdog time-out causes a non-maskable interrupt to the RCPU
1 Software watchdog time-out causes a system reset
Software watchdog prescale
0 Software watchdog timer is not prescaled
1 Software watchdog timer is prescaled by 2048
Figure 6-26. System Protection Control Register (SYPCR)
18
2
1111_1111
19
3
BMT
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 6-15. SYPCR Bit Descriptions
20
4
21
5
22
6
1111_1111_1111_1111
23
7
0x2F C004
SWTC
BME
24
Description
0
8
25
9
000
—
10
26
11
27
SWF SWE SWRI SWP
12
28
0
Freescale Semiconductor
13
29
1
14
30
1
LSB
15
31
1
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