mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 108

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
function of the bus clock, such that the ECLKDIV determination must take this information into account.
If we define:
For example, if the oscillator clock is 950 kHz and the bus clock is 10 MHz, ECLKDIV bits EDIV[5:0]
must be set to 4 (binary 000100) and bit PRDIV8 set to 0. The resulting EECLK is then 190 kHz. As a
result, the EEPROM algorithm timings are increased over optimum target by:
Command execution time will increase proportionally with the period of EECLK.
If the ECLKDIV register is written, the bit EDIVLD is set automatically. If this bit is 0, the register has
not been written since the last reset. EEPROM commands will not be executed if this register has not been
written to.
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EECLK as the clock of the EEPROM timing control block
Tbus as the period of the bus clock
INT(x) as taking the integer part of x (e.g., INT(4.323)=4), then ECLKDIV register bits PRDIV8
and EDIV[5:0] are to be set as described in
Because of the impact of clock synchronization on the accuracy of the
functional timings, programming or erasing the EEPROM cannot be
performed if the bus clock runs at less than 1 MHz. Programming the
EEPROM with an oscillator clock < 150 kHz must be avoided. Setting
ECLKDIV to a value such that EECLK < 150 kHz can reduce the lifetime
of the EEPROM due to overstress. Setting ECLKDIV to a value such that
(1/EECLK+Tbus) < 5 s can result in incomplete programming or erasure
of the memory array cells.
MC9S12HZ256 Data Sheet, Rev. 2.05
200 190
–
CAUTION
200 100
Figure
3-17.
=
5%
Freescale Semiconductor