mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 165

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4
consecutive samples of an active level directly or indirectly
The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock
is generated by a single RC oscillator in the port integration module. To maximize current saving the RC
oscillator runs only if the following condition is true on any pin:
Sample count <= 4 and port interrupt enabled (PIE=1) and port interrupt flag not set (PIF=0).
4.6.2
4.6.3
All clocks are stopped in STOP mode. The port integration module has asynchronous paths on port AD to
generate wake-up interrupts from stop mode. For other sources of external interrupts refer to the respective
block description chapters.
Freescale Semiconductor
Interrupt Sources
Operation in Stop Mode
Vector addresses and their relative interrupt priority are determined at the
MCU level.
Interrupt
Port AD
Source
Table 4-43. Port Integration Module Interrupt Sources
PIFAD[7:0]
Interrupt
MC9S12HZ256 Data Sheet, Rev. 2.05
Figure 4-58. Pulse Illustration
Flag
NOTE
t
pulse
PIEAD[7:0]
Enable
Local
Chapter 4 Port Integration Module (PIM9HZ256V2)
Global (CCR)
Mask
I Bit
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